Material properties analysis of graphene base transistor (GBT) for VLSI analog circuits design

Graphene base transistor’s (GBT) analysis has been reviewed in this paper. This study has been focused on work carried out by other authors for GBT physics. Here prominence has been given to material properties and their effects on GBT for VLSI analog circuit design to operate in high frequency range of THz. Various papers in literature have been reported for the implementation of designs with different emitter and collector materials. Materials properties are the controlling parameters to decide cut-off frequency (f­T), trans-conductance, gain and off current (Ioff) in GBT. The implemented results of literatures signify that the electron affinity and work function of emitter and collector are the dominant factors for flow of charges from emitter to collector. Dependency of these two parameters on dielectric constant and thickness of emitter-base insulator (EBI) and base collector insulator (BCI) that are tantalum pentoxide (Ta2O5), carbon-doped silicon oxide (SiCOH) and SiO2 has been studied. Effects of collector and BCI thickness have been investigated in detail to scrutinize base leakage current by the virtue of back scattering in collector-BCI interface. Small signal equivalent circuit model for GBT have also been studied by including parasitic capacitance behaviour between graphene Dirac-point potential with respect to graphene fermi level, emitter, EBI, BCI and collector fermi level potential

Thermal stability analysis and performance exploration of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET for high performance circuit applications

This paper explores the performance of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET (device-D1) over the wide temperature range (200 K-450 K). An attempt has been made to find out the zero temperature coefficient (ZTC) biased point to enhance the digital, analog and RF performance at 20 nm channel length. The proposed device will be suitable for VLSI circuit’s design, internet of things (IoT) interfacing components and algorithm development for security applications of information technology. The potential parameters of device-D1 like intrinsic gain (AV ), output conductance (gd ), transconductance (gm ), early voltage (VEA ), off current (Ioff) , on current (Ion), Ion/Ioff ratio, gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), energy (CV2), intrinsic delay (CV/I), energy-delay product (EDP), power dissipation (PD), sub-threshold slope (SS), Q-Factor (gm,max/SS), threshold voltage (Vth) and maximum trans-conductance (gm,max) are subjected to analyze for evaluating the performance of ADKUS SOI FinFET for wide temperature environment. The validation of a temperature based performance of ADKUS SOI FinFET gives an opportunity to design the numerous analog and digital components of internet security infrastructure at wide temperature environment. These ADKUS SOI FinFET based components give new technology to the IoT which has the ability to connect the real world with the digital world and enables the people and machines to know the status of thousands of components simultaneously

An Enhanced Approach for Image Edge Detection Using Histogram Equalization (BBHE) and Bacterial Foraging Optimization (BFO)

The Edge detection is a customarily task. Edge detection is the main task to perform as it gives clear information about the images. It is a tremendous device in photograph processing gadgets and computer imaginative and prescient. Previous research has been done on moving window approach and genetic algorithms. In this research paper new technique, Bacterial Foraging Optimization (BFO) is applied which is galvanized through the social foraging conduct of Escherichia coli (E.coli). The Bacterial Foraging Optimization (BFO) has been practice by analysts for clarifying real world optimization problems arising in different areas of engineering and application domains, due to its efficiency. The Brightness preserving bi-histogram equalization (BHEE) is another technique that is used for edge enhancement. The BFO is applied on the low level characteristics on the images to find the pixels of natural images and the values of F-measures, recall(r) and precision (p) are calculated and compared with the previous technique. The enhancement technique i.e. BBHE is carried out to improve the information about the pictures

Study of parametric variations on hetero-junction vertical t-shape TFET for suppressing ambipolar conduction

478-485This paper investigates a hetero-junction vertical t-shape tunnel field effect transistor and discussed various methods for the suppression of ambipolar conduction for the first-time utilizing computer aided design sentaurus simulation tool. This device is primarily consisting of dual gate silicon based gated p-i-n diode for eminent control over the channel. Further, introduction to the 10 nm silicon germanium layer to the channel makes aggressive improvement to the device characteristics. Unlike to the conventional TFET, we have considered the effective techniques like gate-on-drain overlapping, gate-on-channel underlapping and different drain doping concentration up to 1 × 1018 cm−3, which are used to conquer the ambipolar conduction by increasing the tunneling barrier width at the drain channel edges. The device surface potential performance is also analyzed for different parameters like drain doping concentration, gate-source voltage, silicon germanium Si1-xGex mole fraction x and gate oxide thickness. Moreover, the vertical and lateral electric field inspect for determining the tunneling rate. The path distribution of source channel and drain in vertical direction will increase the scalability of the simulated device

Real Time Implementation of Amphibious Unmanned Aerial Vehicle System for Horticulture

Automating the tasks that require manpower has been considered as an area of active research in science and technology. Challenges in designing such systems include accuracy in the parameters of performance, minimal hardware, cost-efficiency, and security. The efficiency of drones designed for replacing humans is often evaluated using their weight, flying time, and power consumption. Herein, the prototype-based Drone model has been designed and discussed for horticulture applications. In this model, a horticulture drone has been designed for structuring and cutting of plants in street interstates. This methodology focuses on automation engineering that is utilized for cutting the plants in less time and less power, thereby diminishing the contamination that may happen by utilizing fuels. The epic part of this plan includes the less weight drone predesigned using Computer-Aided Three-Dimensional Interactive Application (CATIA) V5 Software. The throttle for the motors is adjusted at 50% to get the required thrust for the Unmanned Aerial Vehicle (UAV) to fly. Experimental results show that the horticulture drone has comparatively more flying time and less power consumption.Keywords— CATIA; UAV; Automation; Thrust; Throttle

Study of parametric variations on hetero-junction vertical t-shape TFET for suppressing ambipolar conduction

This paper investigates a hetero-junction vertical t-shape tunnel field effect transistor and discussed various methods for the suppression of ambipolar conduction for the first-time utilizing computer aided design sentaurus simulation tool. This device is primarily consisting of dual gate silicon based gated p-i-n diode for eminent control over the channel. Further, introduction to the 10 nm silicon germanium layer to the channel makes aggressive improvement to the device characteristics. Unlike to the conventional TFET, we have considered the effective techniques like gate-on-drain overlapping, gate-on-channel underlapping and different drain doping concentration up to 1 × 1018 cm−3, which are used to conquer the ambipolar conduction by increasing the tunneling barrier width at the drain channel edges. The device surface potential performance is also analyzed for different parameters like drain doping concentration, gate-source voltage, silicon germanium Si1-xGex mole fraction x and gate oxide thickness. Moreover, the vertical and lateral electric field inspect for determining the tunneling rate. The path distribution of source channel and drain in vertical direction will increase the scalability of the simulated device

Design and Analysis of Various Solar Cell Technologies for Improvements in Efficiencies

Solar energy is an inexhaustible source of energy existing on earth. Sun annually delivers approximately 10,000 times of energy that human race currently exploits. Being neat and clean, solar energy has steered path to redeem utilization of conventional resources of energy by birth of solar cells. Solar cells, modules and Photovoltaic systems have been industrialized substantially since race to conquer outer space started during 1960s. Further, oil crisis in 1970s forced the nations to embrace solar technologies as alternative means for conventional sources of energy. Developments in cost efficacy, compact constructions, consistency and lifetime enabled photovoltaics to be the first option for extensive range of uses in day to day life. Photovoltaics are widely used in telecommunications, remote power and cathodic protection. Objective of this paper is to review developments of solar cells since its origin, with comprehensive description of manufacturing processes, implementations and power conversion efficiencies of solar cells of various generations including their future trends and aspects

A comprehensive Analysis of Nanoscale Transistor Based Biosensor: A Review

Imperative introduction of biosensor in the field of medicine, defence, food safety, security and environmental contamination detection acquired paramount attraction. Thus the foundation of the fame of biosensors in detecting wide scope of biomolecules in innumerable fields has driven researchers in advancement of biosensor and enhancing more updates in devices. Among all semiconductor-FET based biosensors grab attraction due to their miniaturization,mass production, ultra-sensitive in nature, improved lifetime, rapid response and reduce thermal budgets. In this review, field effect based biosensors sensitive to ions their principle model along with pros and cons of different structures. Various performance characteristics for semiconductor based biosensor are explored along with detection of label free analytes such as tuberculosis, glucose, antigen 85-B with ISFET. Following with comprehensive detail on MOSFET junction less Silicon based Dual Gate Biosensor with their design parameters for biosensing of neutral and charged analytes with results summarized in table. Drawbacks of dual gate structure introduce cylindrical structures summarized in table with device parameters and respective sensitivity. Role of analytes size in choosing the cavity width and position of analytes influence the sensitivity is recorded. Recent advancement on selectivity, sensitivity and switching results the gate and channel engineering thus compound semiconductor came in picture. In last section challenges with solution and importance of III-V compound channel as scope in biosensor with taking the benefits of fabrication of III-V compound MOSFETs. Semiconductor compound properties are summarized in table for various applications in recent use

A comprehensive Analysis of Nanoscale Transistor Based Biosensor: A Review

304-318Imperative introduction of biosensor in the field of medicine, defence, food safety, security and environmental contamination detection acquired paramount attraction. Thus the foundation of the fame of biosensors in detecting wide scope of biomolecules in innumerable fields has driven researchers in advancement of biosensor and enhancing more updates in devices. Among all semiconductor-FET based biosensors grab attraction due to their miniaturization, mass production, ultra-sensitive in nature, improved lifetime, rapid response and reduce thermal budgets. In this review, field effect based biosensors sensitive to ions their principle model along with pros and cons of different structures. Various performance characteristics for semiconductor based biosensor are explored along with detection of label free analytes such as tuberculosis, glucose, antigen 85-B with ISFET. Following with comprehensive detail on MOSFET junction less Silicon based Dual Gate Biosensor with their design parameters for biosensing of neutral and charged analytes with results summarized in table. Drawbacks of dual gate structure introduce cylindrical structures summarized in table with device parameters and respective sensitivity. Role of analytes size in choosing the cavity width and position of analytes influence the sensitivity is recorded. Recent advancement on selectivity, sensitivity and switching results the gate and channel engineering thus compound semiconductor came in picture. In last section challenges with solution and importance of III-V compound channel as scope in biosensor with taking the benefits of fabrication of III-V compound MOSFETs. Semiconductor compound properties are summarized in table for various applications in recent use